The inventive concept relates to memory systems and related methods of detecting the distribution of unstable memory cells in memory systems.
Some computers used hard disc drives as a mass storage medium. Hard disc drives can provide large data storage capacities. However, when a hard disc drive receives an external shock, data stored in the disc may be lost. A hard disc drive reads and writes data through a head that is moved by an actuator, where the speed of reading inner portions of the disc is different from the speed of reading outer portions of the hard disc. Solid state discs (SSDs) that use flash memory are increasingly replacing hard disc drives for certain mass data storage applications. Data access speed is faster than in the case of the hard disc drives and, in particular, when several files are simultaneously read.
General memory systems include a memory that stores data, and a memory controller that controls the operation of the memory. A flash memory is a type of semiconductor memory that includes transistor memory cells, i.e., floating gate transistors, which store data. A programming operation is performed by accumulating a predetermined amount of charges in the floating gate. Single bit data or multi-bit data is stored in each memory cell. The memory cell in which the single bit data is stored has two voltage levels defined by the distribution of threshold voltages, and the memory cell in which the multi-bit data is stored has four or more voltage levels.
Single bits, i.e., logic 1 and logic 0, may be represented by a predetermined amount of charge accumulated in a floating gate of a transistor. In other words, a threshold voltage of the transistor is determined by the charges stored in the floating gate. Thus, when a signal at a predetermined voltage level is applied to a gate terminal of the transistor, a turned-on transistor and a turned-off transistor may be discriminated from each other. To read a single bit, a single type of read voltage level can be applied to the gate terminal of the transistor.
When multi-bits such as logic 00, 01, 10, and 11 are represented, the amount of charges to be accumulated on the floating gate should be divided into three types, and thus, three types of read voltage levels are needed. The charges that are stored in the floating gates of a flash memory should vary uniformly within an acceptable range as their mobility changes with temperature variation, stored charge is reduced over time, disturbances occur in adjacent cells during programming operations, and other effects. Thus, the amount of charges to be accumulated on the floating gate is adjusted in consideration of a predetermined margin between voltage levels from the programming operation to read voltage levels.
A basic unit for writing data in a flash memory cell is a page. In order to program a memory cell of the flash memory, a predetermined voltage should be applied to source, drain, gate, and bulk regions. However when power is suddenly turned off while a programming operation is being performed, the data being written may not be adequately stored in the page. The data stored in the page in this state may not be used and may be uncorrectable.
During a page read operation, the memory controller uses an error correction code (ECC) algorithm to determine whether an ECC error or a correctable ECC error is generated in page data. When the memory controller determines that the page is not normally programmed, the memory controller generates an uncorrectable ECC error signal so that the page data may be processed as invalid data. In other words, when it is determined that the page is being programmed before the power supply is cut off and due to the sudden cut off of the power supply, an error is generated, the page is processed as invalid data, and logical block address (LBA) data of a last write request is neglected.
However, when the programming operation is nearly completed, data stored in the page may be corrected. In this case, the memory controller generates a correctable ECC error signal so that the page may be used later. When the programming operation is nearly completed, at least a threshold amount of charge is accumulated on the floating gate. However, when the page is correctable and the data stored in the page is used without being completed, a read error may be generated when the data are read. In this case, since a correctable error signal is generated by the memory controller, a programming operation on the page is not performed later. Thus, the charges accumulated on the floating gate are insufficient.
The amount of charge accumulated on the floating gate may be reduced as a function of reading the stored data and due to natural leakage. When the amount of charge accumulated on the floating gate is not sufficient, data stored in a cell have a different value from the intended valued during the programming operation.
Thus, a method of blocking read errors that may occur when reading data stored in a page for which a programming operation is nearly completed is needed.